This invention is in the field of communications circuitry and systems, and is more specifically directed to digital predistortion techniques in such circuitry and systems.
Wireless data communications have become prevalent in the marketplace over recent years. Wireless access into local area networks (LANs) have become popular in many homes and businesses, especially with advances in higher-speed and longer reach technologies (e.g., according to the recent IEEE 802.11g and 802.11n standards). This trend is continuing, with the development and deployment of wireless broadband access in many locations. Indeed, some cities have recently announced plans to develop and implement municipal wireless broadband access zones within their boundaries. In this regard, the “WiMAX”, “WiBro”, and IEEE 802.16 wireless broadband access technologies are recent technologies and standards for wireless broadband communications and access.
Wireless transceivers, particularly in the wireless data communications context, of course involve power amplifiers that amplify the modulated signals to a sufficient amplitude to successfully transmit these signals. The high data rates desired for broadband communications, for example as specified in the recent wireless broadband technologies, require these power amplifiers to be highly linear in their amplification (i.e., output voltage vs. input voltage). Unfortunately, linearity is typically difficult to achieve in modern wireless power amplifiers, especially in combination with high efficiency operation. Efficiency is of particular importance in mobile wireless broadband communications, to maximize battery life in wireless handsets and to minimize operational costs for wireless basestations.
Digital predistortion is a known method of compensation for power amplifier non-linearity, while still preserving efficiency in the power amplifier operation. In general, digital predistortion digitally distorts the signal to be applied to the input of the power amplifier, based on measurements at the output of the power amplifier. Typically, correction values are generated, based on measurements from the power amplifier output, and are stored in a look-up table (LUT), typically represented in the form of a programmable non-linearity. Digital values of signals to be transmitted are applied as addresses to the LUT to access these correction values, and the accessed correction values “pre-distort” the signals to be transmitted so that the resulting power amplifier output is linear over its dynamic range.
By way of further background, time-domain duplexing (TDD) is a known technique for carrying out wireless communications, or indeed any communications over a communications medium. TDD simply refers to the division of time periods into transmit and receive periods, such that data travels only in one direction (e.g., client equipment to base station) during one period, and travels only in the opposite direction (e.g., base station to client equipment) during the other period.
FIG. 1 illustrates a conventional wireless transceiver architecture for carrying out communications in a TDD environment, and that includes digital predistortion compensation. In this architecture, baseband processor 2 refers to digital circuitry that receives and processes the digital signals to be transmitted and those received, and as such may be in communication with a host processor (not shown), such as the main CPU in a handheld device such as a cellphone or a personal digital assistant (PDA), or in a portable or other computer system. Baseband processor 2 is typically realized as a digital signal processor (DSP) device, for example the DSPs manufactured and sold by Texas Instruments Incorporated.
On the transmit side, baseband processor 2 communicates a digital datastream corresponding to the signals to be transmitted to digital upconverter 4. Digital upconverter 4 is a conventional circuit function that receives the datastream from baseband processor 4, and processes that datastream into a stream of digital samples at a desired sample rate, generally modulated into in-phase and quadrature-phase components as shown in FIG. 1. Digital upconverter 4 also generally includes digital filter and digital mixer functions, as known in the art. In this conventional architecture, the in-phase and quadrature sample streams are applied to digital predistortion function 6, which compensates these sample streams for non-linearity at the power amplifier, as will be described below. In general, digital predistortion function 6 includes a look-up table (LUT) storing compensation values for each available sample amplitude of the input signal from digital upconverter 4, and circuitry that applies the appropriate compensation value from the LUT to the input samples, thus producing compensated in-phase and quadrature-phase values presented to digital-to-analog converters (DACs) 8I, 8Q, as shown in FIG. 1. DACs 8I, 8Q convert the compensated digital sample streams from digital predistortion function 6 into respective analog signals IF_I, IF_Q at a desired intermediate frequency. These intermediate frequency analog signals IF_I, IF_Q are applied to mixer 10TX, which mixes these signals up to a desired carrier frequency generated by local oscillator 11. The resulting mixed analog signal from mixer 10TX is filtered by band-pass filter 11, and applied to the input of power amplifier 12, which in turn drives the signal to be transmitted via duplexer 14 to antenna A.
On the receive side in this conventional architecture, receive mixer 10RX has an input coupled to duplexer 14, and receives signals from antenna A during receive periods, in this TDD architecture. Receive mixer 10RX downconverts the analog frequency of these received signals, producing phase-separated analog signals IF_I, IF_Q at the desired intermediate frequency determined by local oscillator 11. Analog-to-digital converters (ADCs) 18I, 18Q convert these intermediate frequency analog signals IF_I, IF_Q into digital datastreams corresponding to the in-phase and quadrature-phase components, and apply these converted digital signals to digital downconverter 20. As known in the art, digital downconverter 20 performs such functions as downconversion tuning, programmable delay, channel filtering, and automatic gain control on these converted digital signals, along with demodulation of the two components into a single datastream. The resulting datastream from digital downconverter 20 is applied to baseband processor 2, for processing of the received data as appropriate for the particular application.
As mentioned above, the conventional architecture illustrated in FIG. 1 includes digital predistortion, implemented by digital predistortion circuit function 6, to compensate for non-linearity in power amplifier 12. This compensation is effected by accessing correction values corresponding to the amplitude of the digitally upconverted digital signals, for both the in-phase and quadrature-phase components. According to this conventional architecture, as known in the art, the correction non-linearities, typically stored in a LUT within digital predistortion function 6, are derived from measurements of the signal output by power amplifier 12; these correction values are updated over time, in this conventional architecture.
FIGS. 2a through 2c illustrate the theory of operation of digital predistortion compensation, as known in the art and as realized in digital predistortion circuit function 6 in the system of FIG. 1. FIG. 2a illustrates the ideal linear operation of a power amplifier. As shown in FIG. 2a, output voltage Vout exactly equals the input voltage Vin, multiplied by gain k (i.e., Vout=kVin) Real power amplifiers, such as power amplifier 12 in the transceiver of FIG. 1, do not operate with this ideal characteristic, however. Rather, nonlinearities in the operation of conventional power amplifiers, especially in the wireless environment, tend to flatten out the amplifier gain, with the gain typically saturating at high input voltage levels. FIG. 2b illustrates an example of a power amplifier characteristic, in which the output voltage Vout is not merely the input voltage Vin multiplied by gain k, but also includes a multiplicative non-linear function ƒ(Vin) that is also involved in the determination of the output voltage Vout. This non-linearity, which may be expressed as Vout=ƒ(Vin)kVin, is undesirable in transceiver systems, especially in high data rate wireless communications as desired to be carried out by the transceiver of FIG. 1. Digital pre-distortion function 6 therefore applies a corrective factor to the input signals to be amplified, preferably approximating the inverse of the non-linear function ƒ(Vin) applied by power amplifier 12. FIG. 2c illustrates compensated voltage Vcomp as corresponding to inverse function ƒ−1(Vin). It is this compensated voltage Vcomp that is then used as the input to the power amplifier stage, so that the resulting output voltage Vout will in turn be a linear function of the input voltage Vin (i.e., Vout=kVin). By compensating the voltages applied at the input of power amplifier 12 in this manner, the output of power amplifier 12 approaches the ideal characteristic illustrated in FIG. 1a. 
As known in the art, the derivation of the compensation applied by digital predistortion function 4 (i.e., the inverse function ƒ−1(Vin) of FIG. 2c) is based on actual measurements at the output of power amplifier 12. This takes into account the actual characteristics of power amplifier 12, and changes in those characteristics over time and over environmental changes (temperature, etc.) of the system. Referring back to FIG. 1, in this conventional architecture, the output of power amplifier 12 is coupled to mixer 10DPD via coupler 13. Mixer 10DPD generates intermediate frequency analog signals IF_I, IF_Q, shifted in frequency based on the reference signal from local oscillator 11, in the known manner. These intermediate frequency analog signals IF_I, IF_Q are converted to digital signal streams by ADCs 16I, 16Q, respectively, and applied to digital predistortion function 6. As known in the art, circuitry or software functionality within digital predistortion function 6 is readily able to derive compensation values based on the measured signals from the output of power amplifier 12, as compared with the corresponding input values generated by digital upconverter 4. In operation, digital predistortion function 6 receives the feedback signal via the loop of mixer 10DPD and ADCs 16 during TDD transmission periods, and uses this feedback to determine and adjust the predistortion correction values.